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1 ABBREVIATIONS

DAC Digital to Analog Converter
ESD Electrostatic Discharge
FPS Frames Per Second
HSC High-Speed Comparator
I/O Input / Output
LFSR Linear Feedback Shift Register
LSB Least Significant Byte
LSb Least Significant Bit
MSB Most Significant Byte
MSb Most Significant Bit
MUR Maximum Unambiguous Range
NA Not Available
NC Not Connected
PCB Printed Circuit Board
PG Pulse Generator
PRF Pulse Repetition Frequency
QFN Quad-Flat pack No leads
RF Radio Frequency
RX Receive(r)
SD Sample Delay
SPD Send Pulse Delay
SPI Serial Peripheral Interface
TSP Total Sequence Period
TX Transmit(ter)
UWB Ultra Wide Band
VGA Variable Gain Amplifier



DATASHEET
NVA6100 – Preliminary

Novelda Restricted Rev. No: 0.4.1 10.11.2011
www.novelda.no © 2010-2011 Novelda AS Page 5 of 39

2 ABSOLUTE MAXIMUM RATINGS
Note that the absolute maximum ratings are stress ratings, and functional operation of the device under
such conditions is not guaranteed. Long-term exposure to absolute maximum rating conditions may
affect device reliability, and permanent damage may occur if these ratings are violated.

Parameter Min. Max. Unit
Supply voltage core, VDDD, VDDA_TH, VDDA_TIMINGCTRL -0.3 1.26 V
Supply voltage I/O, VDDD25_IO, VDDA25_DAC -0.3 2.75 V
Input voltage, digital I/O -0.3 3.6 V
Input RF level 6 dBm
Storage temperature -65 150 ºC
Reflow solder temperature 260 ºC


Table 1. Absolute maximum ratings.

Caution! This is an electrostatic sensitive device.
Failure to observe proper handling and installation
procedures may result in performance degradation or
terminal damage to the device.


3 ELECTRICAL CHARACTERISTICS
If nothing else is noted, all electrical characteristics are measured on the NVA6100 development
modules (NVA-R630 and NVA-R640 respectively).

Important notice. Please be advised that all data
presented in this section are expected performance
characteristics only, and are subject to change at any time,
without further notice.


3.1 GENERAL OPERATING CONDITIONS

Parameter Min. Typ. Max. Unit
Supply voltage core, VDDD, VDDA_TH,
VDDA_TIMINGCTRL
1.14 1.2 1.26 V
Supply voltage I/O, VDD25_IO, VDDA25_DAC 2.25 2.5 2.75 V
Ambient operating temperature -40 85 ºC
Main clock frequency, fMCLK 100 MHz
SPI clock frequency, fSCLK 25 MHz
Logic input low voltage, VIL -0.3 0.7 V
Logic input high voltage, VIH 1.7 3.6 V
Logic output low voltage, VOL 0.7 V
Logic output high voltage, VOH 1.7 V


Table 2. General operating conditions.
DATASHEET
NVA6100 – Preliminary

Novelda Restricted Rev. No: 0.4.1 10.11.2011
www.novelda.no © 2010-2011 Novelda AS Page 6 of 39

3.2 TRANSMITTER
3.2.1 IPG0, M
EDIUM-BAND PULSE GENERATOR

Parameter Min. Typ. Max. Unit Note
Order of Gaussian pulse approximation 1
Lower -10 dB cutoff frequency, fL
Slow
Nominal
Fast
620
780
880
660
845
1060
690
890
1150
MHz
MHz
MHz
1
Upper -10 dB cutoff frequency, fH
Slow
Nominal
Fast
6960
9180
10300
7145
9550
10410
7300
9735
10600
MHz
MHz
MHz
1
Nominal output power -19 dBm 2,3
Instantaneous output amplitude
Slow
Nominal
Fast
440
430
340
470
450
370
510
480
410
mV
mV
mV
1
TSP for staggered PRF 65535 pulses
Staggered PRF step resolution 33.8 ps 4


Table 3. Medium-band pulse generator characteristics.
3.2.2 IPG1, LOW-BAND PULSE GENERATOR

Parameter Min. Typ. Max. Unit Note
Order of Gaussian pulse approximation 1
Lower -10 dB cutoff frequency, fL
Slow
Nominal
Fast
420
445
480
435
450
485
440
460
495
MHz
MHz
MHz
1
Upper -10 dB cutoff frequency, fH
Slow
Nominal
Fast
3115
3490
3970
3165
3555
4065
3230
3635
4150
MHz
MHz
MHz
1
Nominal output power -14 dBm 2,3
Instantaneous output amplitude 450 500 550 mV 5
TSP for staggered PRF 65535 pulses
Staggered PRF step resolution 33.8 ps 4


Table 4. Low-band pulse generator characteristics.
1
The pulse generator’s frequency band is programmable in 3 steps: slow, nominal and fast.
2
Measured at -10 dB output bandwidth, delivered to a single ended 50 Ω load.
3
PRF = 48 MHz.
4
Expected performance. Inferred from frame offset MediumTune measurements.
5
Output amplitude of IPG1 is unaffected by bandwidth settings.
DATASHEET
NVA6100 – Preliminary

Novelda Restricted Rev. No: 0.4.1 10.11.2011
www.novelda.no © 2010-2011 Novelda AS Page 7 of 39

3.3 RECEIVER

Parameter Min. Typ. Max. Unit Note
Receiver sensitivity
Gain 0/1
Gain 2/3
Gain 4
Gain 5/6
-73
-80
-90
-95
dBm
dBm
dBm
dBm
1
Dynamic range dB 2
Programmable input amplifier gain range 29 dB 3
Input threshold resolution 13 bits
Samples per frame 512 samples 4
Equivalent programmable sampling rate
Sampling rate 0
Sampling rate 1
Sampling rate 2
32.0
17.0
39.0
20.0
3.8
42.0
21.5
GS/s
GS/s
GS/s
5
Minimum frame offset (trigger delay) -350 ns
Maximum frame offset (trigger delay) 350 ns
Frame offset step, CoarseTune 0.90 1.10 1.30 ns 5,6
Frame offset step, MediumTune 30.0 33.8 44.0 ps
Frame offset step, FineTune 1.3 1.7 2.2 ps


Table 5. Receiver characteristics.
3.4 POWER CONSUMPTION

Parameter Min. Typ. Max. Unit Note
Power consumption 116 mW 2


Table 6. Power consumption characteristics.
1
Receiver sensitivity at 10 dB SNR. Radar Settings were as follows: DACMin = 4014, DACMax = 4178,
PulsesPerStep = 100, Iterations = 10.
2
No or only partial data available at the time of writing.
3
Input amplifier gain is programmable in 7 steps, from -6 to 23 dB.
4
Downsampling enables selectable frame sizes of 512, 256, 128 or 64 samples.
5
Both sampling rate and frame offset delays are dependent on PRF. A calibration circuit is included for
measuring and calibrating these delays. Please refer to Section 12 for details.

6
PRF = 20 MHz.
DATASHEET
NVA6100 – Preliminary

Novelda Restricted Rev. No: 0.4.1 10.11.2011
www.novelda.no © 2010-2011 Novelda AS Page 8 of 39

4 PIN ASSIGNMENT
Figure 1. NVA6100 pinout, top view QFN32 package.
4.1 TERMINAL FUNCTIONS

Pin Pin name Pin type Description
- GNDD Ground (digital) Exposed die pad. Provides ground connection
for the digital core. Must be connected to a
solid ground plane.
1 IBIAS_DAC Analog I/O Reference current for internal DAC.
2 GNDA_DAC Ground (analog) DAC ground connection.
3 GNDA_DAC Ground (analog) DAC ground connection.
4 VDDA25_DAC Power (analog) DAC power supply (2.5 V).
5 VDDA25_DAC Power (analog) DAC power supply (2.5 V).
6 VTHOUT Digital output Threshold output for debugging purposes.
7 VDDA_PWDN_TH Power (analog) Input thresholder power supply (1.2 V) for
powerdown function.
8 GNDA_TH Ground (analog) Input thresholder ground connection.
9 VDDA_TH Power (analog) Input thresholder power supply (1.2 V).
10 GNDA_TH Ground (analog) Input thresholder ground connection.
11 RFIN RF input RF input from receiving antenna.
12 GNDA_TH Ground (analog) Input thresholder ground connection.
13 VDDA_TH Power (analog) Input thresholder power supply (1.2 V).
14 NC - Not connected.
15 VDDD Power (digital) Digital core power supply (1.2 V).
16 VDDD Power (digital) Digital core power supply (1.2 V).



DATASHEET
NVA6100 – Preliminary

Novelda Restricted Rev. No: 0.4.1 10.11.2011
www.novelda.no © 2010-2011 Novelda AS Page 9 of 39

Pin Pin name Pin type Description
17 VDDD Power (digital) Digital core power supply (1.2 V).
18 MISO Digital output SPI Master In Slave Out.
19 MOSI Digital input SPI Master Out Slave In.
20 SCLK Digital input SPI Clock input.
21 nSS Digital input SPI Slave Select (active low).
22 MCLK Digital input Master Clock input.
23 GNDD_IO Ground (digital) Digital I/O post-driver ground connection.
24 VDDD25_IO Power (digital) Digital I/O post-driver power supply (2.5 V).
25 VDDA_TIMINGCTRL Power (analog) Power supply (1.2 V) for analog parts of timing
controller and high-speed sampler.
26 GNDA_TIMINGCTRL Ground (analog) Ground connection for analog parts of timing
controller and high-speed sampler.
27 MCLK_DELAYED_OUT Digital output Clock output with programmable delay.
28 VDDD Power (digital) Digital core power supply (1.2 V).
29 RFOUT_IPG0 RF output Medium-band impulse generator RF output.
30 RFOUT_IPG1
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